SRAM-based 4-bit MAC unit

Full handout: course project handout.

Before the bitcell, the Cadence environment is checked out with a sample inverter (proj1_lib sample_inv).

Part 1 numbers on this site that come from Quantus are extracted. Part 2 and Part 3 timing, energy and area (except the tiled cell) are schematic-level or \(D\sum W_i L_i\) estimates and are labeled as such. A hand estimate never stands in for a measured Spectre integral.

At fixed nominal length, a simple resistance model gives:

At 0.8 V this predicts 0.400, 0.320 and 0.267 V for β=1, 1.5 and 2. These are hand estimates. The measured DC zero-node crossings are 0.134, 0.097 and 0.077 V; the resistor approximation overestimates them because MOS device resistance varies with voltage. It correctly predicts that stronger PD reduces the disturb.

With \(E=V_{DD}-V_{Tn}\), the idealized saturated PG and triode PD currents are:

At DC equilibrium \(I_{PG}=I_{PD}\). The physical root is \(V_Q=E(1-\sqrt{\beta/(1+\beta)})\). This long-channel model assumes equal NMOS thresholds, negligible body effect and the stated operating regions. It is a guide to the trend, not a substitute for GPDK simulation.

The disturbed Q node drives the opposite inverter. Read stability requires \(V_Q<V_M\), where \(V_M\) is that inverter’s switching point. In a square-law approximation, \(V_M=(V_{Tn}+B(V_{DD}-|V_{Tp}|))/(1+B)\) with \(B\approx\sqrt{\gamma\mu_p/(\beta\mu_n)}\). Since \(V_M\) was not separately measured, the actual read-margin comparison is the butterfly result.

The original detailed write analysis treats the pass-gate as triode and the pull-up as saturated while \(V_Q<|V_{Tp}|\). Let \(E=V_{DD}-V_{Tn}\) and \(F=V_{DD}-|V_{Tp}|\). Equating the two branch currents yields:

The other quadratic root conflicts with the assumed pass-gate region; this expression also ceases to apply when PU enters triode. The completed manuscript retains the full typed derivation. No separate handwritten write image is present in media/part1/, so the site does not invent one.

The β=2, γ=1 candidate still needs the handout’s write-margin sweep: store Q=1, hold the opposing bitline high, sweep the write-zero bitline down from VDD, and record its flip voltage. A stronger PG can improve write ability but weaken read stability and increase bitline load; the read sweep alone cannot close that trade-off.

For each β, the read bench holds WL, BL and BLB at VDD=0.8 V. One DC bench sweeps Q and records QB; the other sweeps QB and records Q with feedback broken. The two original Virtuoso testbench captures below document the biasing and signals used.

The four-column ViVA raw.csv for each β is split into q.csv and qb.csv; one curve is reflected about \(y=x\). scripts/check_snm_sweep.py finds the three intersections and fits the largest voltage square in each butterfly lobe. The smaller lobe side is \(SNM_{read}\). Its final 16,001-point computation differs from a 4,001-point check by at most 0.05 mV.

At the handout’s two-significant-figure precision, read SNM is 0.13, 0.15 and 0.16 V; the disturbed zero-node crossings are 0.13, 0.097 and 0.077 V. The table retains extra digits to trace the calculations.

The low-voltage crossing is the reported DC zero-node read-disturb operating point. The β=2 schematic improves read SNM by 29.7 mV (23%) over β=1 at 0.8 V, while lowering that crossing by 57.2 mV.

These are the original Cadence screenshots. Cyan outlines are drawn by this report/site at the square positions stored in each snm.json. The ViVA x and y axes have unequal pixel scales, so a square in volts appears rectangular on the screenshot. The outlines are computed annotations, not an indication that Cadence directly reported SNM. All three captures preserve the original trace colors and axes.

On a phone, swipe the captures sideways to inspect the full axes and overlays.

results/part1/read-snm/beta*/raw.csv is the verbatim ViVA export. The normalized q.csv and qb.csv, computed snm.json and clean butterfly PNG/SVG are reproducible derivatives. Run:

The clean plots are secondary reading aids; the screenshots above are the original Cadence view. This sweep is schematic. The extracted read SNM that supersedes 156.3 mV is 140 mV, in post-layout stability.

The drawn cell keeps the schematic sizes: L=18 nm, pull-ups at 2 fins, pull-downs at 4 fins, pass-gates at 2 fins.

Mirrored neighbours can share the VDD rail, the VSS rail, and the bitline contacts. The PR boundary is 0.72 µm by 0.54 µm.

The area is the PR-boundary area that abutting cells repeat. It includes the half-rails and half-bitline contacts shared with mirrored neighbours.

The handout estimates un-laid-out blocks as \(A_{\mathrm{est}}=D\sum_i W_i L_i\), with \(D\) measured on this cell. One fin counts as the PDK fin pitch, \(W_{\mathrm{fin}}=48\,\mathrm{nm}\), and \(L=18\,\mathrm{nm}\) on every device. The cell has 16 fins, so

The same fin-pitch convention has to be used for every \(\sum W_i L_i\) in Parts 2 and 3.

Parasitics come from the layout with the tutorial Quantus flow (C+CC).

The bitline term is the pass-gate drain junction plus the shared bitline contact. The wordline term is two pass-gate gates plus the WL wire across the cell. Fifteen copies of 180 aF are the stand-in column load in the functional check.

These benches use the extracted view. The margin is the same largest-square reduction as the schematic sweep. If the butterfly is asymmetric, SNM is the smaller side.

Extraction lowers read SNM from the schematic 156.3 mV to 140 mV and raises the disturbed zero node from 77.1 mV to 95 mV. Hold SNM, 280 mV, stays well above the read margin.

Read SNM falls from 140 mV to 110 mV to 70 mV as the supply drops. \(\mathrm{WM}_{BL}\) falls from 0.42 V to 0.32 V to 0.18 V. At 0.5 V the cell still reads. The write is the weak result: 0.18 V is still a trip point, and it is the smallest margin in the table.

The transient bench drives WL and the precharge devices with ideal pulses and loads each bitline with the extracted cell plus 15 copies of 180 aF, standing in for a 16-row column. The sequence is write 0, read, write 1, read. The capture (media/part1/functional_check.png) is not in the repository yet.

Read stability is set by the pass-gate/pull-down divider. The schematic sweep moved the disturbed zero node from 134 mV (β=1) to 77 mV (β=2). Extraction gives 140 mV of read SNM and a 95 mV zero node at 0.8 V, against a hold SNM of 280 mV, so the read is what the Part 2 noise budget has to clear. The four-fin pull-down sets the 0.54 µm cell height and most of \(C_{WL}=90\) aF. The two-fin pass-gate sets \(C_{BL}=180\) aF and the 25 µA read current. Writability is the γ=1 limit: \(\mathrm{WM}_{BL}\) is 0.42 V at 0.8 V and 0.18 V at 0.5 V. The cell still reads at 0.5 V (70 mV). The write is the weak one, so a Part 2 remedy, if that margin is not enough for the column, is a weaker pull-up or a write assist rather than a new cell. Part 2 keeps this cell, mirrors it to share the BL contacts and the VDD/VSS rails, and sizes the wordline driver and precharge from 16 × 180 aF and 4 × 90 aF plus wire.

Both authors are responsible for the complete design and report.

Write driver NMOS stacks are nfin=8 (smallest that writes at 3.5 fF is nfin=5; nfin=8 writes in 96 ps with BLB staying above ~0.34 V). Minimum write pulse at 50% is 100–120 ps; design pulse ~140 ps.

Precharge is three 2-fin PMOS per column. Read path is a 2:2 inverter into an output latch enabled on the clock-high phase (see Part 3 for the RD_EN fix on tb_top).

Chosen decoder is a 2–2 predecode (NAND3 + inv_2x + row NAND2 + inv_drv). Logical effort with B=8 (address fan-out) predicts 182 ps address-to-wordline (\(\tau=10.5\) ps from FO4=53 ps). Measured A⟨0⟩ path: 106 ps (new row rising) / 112 ps (old row falling).

tb_sram_macro writes 16 words, reads them, writes the complement, and reads again. err1 / err2 / err3 (M-weighted DOUT error) all pass at 173.8 µV against a 0.1 V spec. Worst-case access at \(T_{CLK}=0.69\) ns is 488 ps on a read of 1.

Clock-running idle (112.2 µW) is almost the read power (115.2 µW): the delay-chain controller has no chip-select, so SRAM energy in Part 3 is nearly pattern-independent.

Positive-edge TG master-slave (d_ff), 100 fins, fully static so IDLE and DONE can stop the clock. \(C_Q=1\) fF, 0.4 V markers.

Leaf cells are static CMOS, L=18 nm. The 4×4 array multiplier is AND rows plus ripple full adders. Exhaustive 256/256 products match; measured worst case is 1.14–1.24 ns (vector 244, B=15). Hand logical effort is ~1.85 ns. The 12-bit ripple adder is twelve of the same full adder (148 fins each).

controller_mac plus counter_4b: START is sampled on a rising CLK; COUNT walks 0–15; both macros are read in cycles 0–15; VALID delays ACC_EN so accumulate occupies cycles 1–16; DONE rises on cycle 17. tb_controller_mac: 60/60 vector checks; tb_counter4b: 38/38.

Expected finals: A = 0x34D (845), B = 0xE10 (3600, full-scale carries), C = 0x320 (800, 5/10 checkerboard). Vectors in stimuli/timing/mac_top_<A|B|C>_<period>.vec.

The first tb_top runs finished DONE with ACC = 0: RD_EN was a ~150 ps pulse that closed before RD crossed mid-rail. RD_EN is now CLKBUF · not WE_L (level-sensitive on clock-high). Tests A–C after the fix are the check.

Single VDD pin on tb_top. Window 82–126 ns (44 ns clip; latency is 42.5 ns).

Memory vs logic is not a second Spectre split (one VDD). From Part 2: \(E_{\mathrm{macro/cyc}}\approx86.7\) fJ at 2.5 ns → \(E_{\mathrm{mem}}\approx2.77\) pJ (est.) for two macros × 16 addresses. Test A logic ≈ 6.10 pJ (0.38 pJ/MAC without memory, est.). Bitline restore is only 0.29 pJ of that 2.77 pJ; the clocked Part 2 controller dominates.

reported as \(1.1\times10^{5}\) µm²·pJ·ns.

The period is set by the multiply-accumulate path (~1.2 ns multiplier, then 12-bit ripple and \(t_{su}=40\) ps), not the 488 ps SRAM read. Ripple arithmetic was kept for one verified full adder. A chip-select on the macros would cut the clocked memory energy; a pipeline register after the multiplier would split SRAM and arithmetic at a second extra cycle (18).

Raw 4-col SNM exports live in results/part1/read-snm/beta*/raw.csv. Part 2 notes: results/sram_macro_unit_test.md, results/sram_macro_area_fom.md. Part 3 figures: report/part3/img/.

Class of 2028, Computer Engineering, University of Pennsylvania.

Class of 2028, Computer Engineering, University of Pennsylvania.