tmarhguy
[](https://linkedin.com/in/tmarhguy) [](mailto:tmarhguy@seas.upenn.edu) [](https://tmarhguy.com) [](https://github.com/tmarhguy)
About
I build complete systems that cut across hardware and software — from discrete‑transistor arithmetic units and ASIC tapeouts to full‑stack web applications. I care about first‑principles understanding, verification, and shipping things that actually run on real hardware.
- Computer Engineering at Penn Engineering (UPenn)
- Focus: digital design, VLSI, RISC‑V, embedded systems, and performance‑sensitive backends
- Grew up in Ghana; won a constitutional case on religious freedom that is now widely covered and cited
Flagship Hardware · 8‑Bit Discrete Transistor ALU
Live site: alu.tmarhguy.com · Code: github.com/tmarhguy/alu
- 3,488 discrete MOSFETs, hand‑soldered on a 4‑layer PCB
- 19 operations with status flags (arithmetic and logical)
- More than 1.24M automatically generated test vectors driven by Python
- Validated through KiCad schematics, SPICE simulation, and a custom digital testbench
- Full breakdown and interactive visualization on the companion site
This project sits at the intersection of circuit design, tooling, and verification at scale.
Selected Projects
Silicon and Systems
-
16‑bit MAC Unit (Sky130 ASIC) · Repo: github.com/tmarhguy/mac
- BFloat16 MAC designed for ML‑style workloads, targeting the SkyWater 130 nm node
- Full OpenLane RTL‑to‑GDS flow (synthesis, floorplan, CTS, routing)
- Closed timing at 50 MHz with zero DRC/LVS violations in a 0.11 mm² die
-
64‑bit RISC‑V CPU (RV64IM) · Repo: github.com/tmarhguy/riscv
- Custom 5‑stage pipelined core (RV64IM) on an Artix‑7 FPGA
- Verified against the official riscv‑tests suite with 96 percent ISA coverage
- Runs bare‑metal C via a UART bootloader, with custom peripheral controllers
Software and Data Systems
-
UniBridge Ghana – Admissions Platform · Repo: github.com/tmarhguy/unibridgeGhana
- Centralized university admissions and placement platform
- React and TypeScript frontend with a FastAPI and PostgreSQL backend
- Designed to handle result‑release traffic spikes with predictable latency
-
MoMo Credit Score Generator · Repo: github.com/tmarhguy/momo-credit-score
- Credit‑scoring engine built on mobile money transaction data
- XGBoost model with an AUC around 0.82 on internal evaluation
- FastAPI backend and React dashboard, with feature‑level explanations
-
SVD Compression Engine · Demo: svd.tmarhguy.com · Repo: github.com/tmarhguy/svd
- Singular Value Decomposition based image compression
- Implementation tuned for cache behaviour and matrix‑math performance
- Achieves a measured speedup of roughly 45 percent over a naive baseline
For a fuller, visually rich overview of these and more projects, see the portfolio site: tmarhguy.github.io/tmarhguy.
Skills
Hardware and Digital Design
- Verilog and SystemVerilog, RTL design, timing closure
- ASIC flow with OpenLane and the Sky130 process, Magic, KiCad PCB layout
- FPGA bring‑up on Artix‑7, basic signal‑integrity and power analysis
Software and Backend
- Languages: TypeScript, Python, C and C++
- Frameworks: React, FastAPI, Node.js
- Data and ML: NumPy, pandas, scikit‑learn, XGBoost
Practices
- Test‑driven development for both RTL and software
- Automated verification with Python harnesses and simulation tools
- Continuous integration, containerisation, and reproducible environments
Recognition
Work on both the constitutional case and academic achievements has been covered or cited by outlets including:
GitHub stats
Contact
Building bridges between silicon and software, one verified system at a time.